Memory devices typically are composed of an array of bit cells, with each bit cell storing a corresponding bit of data. Each bit cell generally is configured as one or more transistors that store or retain an electrical charge representative of a bit value (e.g., a logic “0” or a logic “1”). As a result of errors in the fabrication process, a subset of the bit cells of the memory device may be determined to be defective. To compensate for the likely occurrence of defective bit cells, memory devices typically implement redundant bit cells (typically arranged as redundant rows, redundant columns, redundant sectors, and combinations thereof). The memory devices typically use a fuse array or logic to reroute an memory address associated with a portion of bit cell array having a defective bit cell to a corresponding portion of the redundant bit cells (e.g., rerouting a memory address to a row having a defective bit cell to a redundant row of bit cells). However, while these techniques compensate for the operational failure of the defective bit cells, these defective bit cells often continue to draw power during operation. In certain instances, the same defect that causes a bit cell to fail functionally also results in a short in the bit cell, which can sink substantial current and cause operational failure of the entire memory device during low power states, such as while the memory device is in a sleep mode. Accordingly, an improved technique for compensating for defective bit cells in a memory device would be advantageous.
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